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LH28F016LL
FEATURES
16M (1M x 16, 2M x 8) Flash Memory
56-PIN TSOP
TOP VIEW
* User-Configurable x8 or x16 Operation * 3 V Write/Erase Operation (3 V VPP)
- 2.7 - 3.6 V Write-Erase Operation
VSSL CE1 LX A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 CX RP A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
WP WE OE RY/BY DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE NC NC
* 120 ns Maximum Access Time
(VCC = 3.0 V)
* 150 ns Maximum Access Time
(VCC = 2.7 V)
* * * *
32 Independently Lockable Blocks (64K) 0.48 MB/sec Write Transfer Rate 100,000 Erase Cycles per Block Revolutionary Architecture - Pipelined Command Execution - Write During Erase - Command Superset of Sharp LH28F016SU
* 10 A (MAX.) ICC in CMOS Standby * 5 A (MAX.) Deep Power-Down * State-of-the Art 0.6 m ETOXTM
Flash Technology
* 56-Pin, 1.2 mm x 14 mm x 20 mm TSOP
(Type I) Package
28F016LLT-1
Figure 1. TSOP Configuration
1
LH28F016LL
16M (1M x 16, 2M x 8) Flash Memory
DQ8 - DQ15
DQ0 - DQ7
OUTPUT BUFFER
OUTPUT BUFFER
INPUT BUFFER
INPUT BUFFER
ID REGISTER
DATA QUEUE REGISTERS
I/O LOGIC
BYTE
CSR OUTPUT MULTIPLEXER PAGE BUFFERS
ESRs
CE0 CE1 OE CUI WE WP RP
DATA COMPARATOR
A0 - A20
INPUT BUFFER
Y-DECODER
Y GATING/SENSING
64KB BLOCK 30
64KB BLOCK 31
64KB BLOCK 0
64KB BLOCK 1
WSM
RY/BY
ADDRESS QUEUE LATCHES
...
X-DECODER
...
DC/DC CONVERTER PROGRAM/ ERASE VOLTAGE SWITCH
LX CX
ADDRESS COUNTER
...
VCC GND
28F016LLT-2
Figure 2. LH28F016LL Block Diagram (Architectural Evolution Includes Page Buffers, Queue Registers and Extended Status Registers)
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16M (1M x 16, 2M x 8) Flash Memory
LH28F016LL
PIN DESCRIPTION
SYMBOL TYPE NAME AND FUNCTION BYTE-SELECT ADDRESS: Selects between high and low byte when device is in x8 mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the A0 input buffer is turned off when BYTE is high). WORD-SELECT ADDRESSES: Select a word within one 64K block. A6 - A15 selects 1 of 1024 rows, and A1 - A5 selects 16 of 512 columns. These addresses are latched during Data Writes. BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are latched during Data Writes, Erase and Lock-Block operations. LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles. Outputs array, buffer, identifier or status data in the appropriate Read mode. Floated when the chip is de-selected or the outputs are disabled. HIGH-BYTE DATA BUS: Inputs data during x16 Data-Write operations. Outputs array, buffer or identifier data in the appropriate Read mode; not used for Status register reads. Floated when the chip is de-selected or the outputs are disabled. CHIP ENABLE INPUTS: Activate the device's control logic, input buffers, decoders and sense amplifiers. With either CE 0 or CE 1 high, the device is de-selected and power consumption reduces to Standby levels upon completion of any current Data-Write or Erase operations. Both CE 0, CE 1 must be low to select the device. All timing specifications are the same for both signals. Device Selection occurs with the latter falling edge of CE 0 or CE 1. The first rising edge of CE 0 or CE 1 disables the device. RESET/POWER-DOWN: RP low places the device in a Deep Power-Down state. All circuits that burn static power, even those circuits enabled in standby mode, are turned off. When returning from Deep Power-Down, a recovery time of 5 ns is required to allow these circuits to power-up for Read mode, and another 395 ns is required to enter Program or Erase mode. When RP goes low, any current or pending WSM operation(s) are terminated, and the device is reset. All Status registers return to ready (with all status flags cleared). OUTPUT ENABLE: Gates device data through the output buffers when low. The outputs float to tri-state off when OE is high. NOTE: CE X overrides OE , and OE overrides WE. WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers and Address Queue Latches. WE is active low, and latches both address and data (command or array) on its rising edge. READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the WSM is busy performing an operation. RY /BY high indicates that the WSM is ready for new operations (or WSM has completed all pending operations), or Erase is Suspended, or the device is in deep power-down mode. This output is always active (i.e., not floated to tri-state off when OE or CE 0, CE 1 are high), except if a RY /BY Pin Disable command is issued.
A0
INPUT
A1 - A15
INPUT
A16 - A20
INPUT
DQ0 - DQ7
INPUT/OUTPUT
DQ8 - DQ15 INPUT/OUTPUT
CE 0, CE 1
INPUT
RP
INPUT
OE
INPUT
WE
INPUT
RY /BY
OPEN DRAIN OUTPUT
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LH28F016LL
16M (1M x 16, 2M x 8) Flash Memory
PIN DESCRIPTION (Continued)
SYMBOL TYPE NAME AND FUNCTION WRITE PROTECT: Erase blocks can be locked by writing a non-volatile lock-bit for each block. When WP is low, those locked blocks as reflected by the Block-Lock Status bits (BSR.6), are protected from inadvertent Data Writes or Erases. When WP is high, all blocks can be Written or Erased regardless of the state of the lock-bits. The WP input buffer is disabled when RP transitions low (deep power-down mode). BYTE ENABLE: BYTE low places device in x8 mode. All data is then input or output on DQ0 - DQ7, and DQ8 - DQ15 float. Address A0 selects between the high and low byte. BYTE high places the device in x16 mode, and turns off the A0 input buffer. Address A1, then becomes the lowest order address. INPUT FROM OUTSIDE INDUCTOR: Input pin for outside inductor in DC/DC converter circuit. Connect 1.8 (H) inductor from VCC. INPUT FROM OUTSIDE CAPACITOR: Input pin for outside capacitor in DC/DC converter circuit. Ground at 22000 (pF) capacitor. DEVICE POWER SUPPLY 3.0 V (2.7 V to 3.6 V): Do not leave any power pins floating. GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating. NO CONNECT: No internal connection to die, lead may be driven or left floating. GROUND
WP
INPUT
BYTE
INPUT
LX LC VCC GND NC VSSL
INPUT INPUT SUPPLY SUPPLY
4
16M (1M x 16, 2M x 8) Flash Memory
LH28F016LL
INTRODUCTION
Sharp's LH28F016LL 16M Flash Memory is a revolutionary architecture which enables the design of truly mobile, high performance, personal computing and communication products. With innovative capabilities, 3 V single voltage operation and very high read/write performance, the LH28F0166LL is also the ideal choice for designing embedded mass storage flash memory systems. The LH28F016LL is very high density, highest performance non-volatile read/write solution for solid-state storage applications. Its symmetrically blocked architecture (100% compatible with the LH28F016SU 16M Flash memory), extended cycling, minimum power 2.7 V operation, very fast write and read performance and selective block locking provide a highly flexible memory component suitable for battery operation portable equipment such as digital still camera, PDA, cellular phone, and memory card. Its x8/x16 architecture allows the optimization of memory to processor interface. The flexible block locking option enables bundling of executable of executable application software in a Resident Flash Array or memory card. Manufactured on Sharp's 0.6 m ETOXTM process technology, the LH28F016LL is the most cost-effective, high-density 3 V single power operation flash memory.
Internal Algorithm Automation allows Byte/Word Writes and Block Erase operations to be executed using a Two-Write command sequence to the CUI in the same way as the LH28F008SA 8M Flash memory. A Superset of commands have been added to the basic LH28F008SA command-set to achieve higher write performance and provide additional capabilities. These new commands and features include:
* * * * * *
Page Buffer Writes to Flash Command Queuing Capability Automatic Data Writes During Erase Software Locking of Memory Blocks Two-Byte Successive Writes in 8-bit Systems Erase All Unlocked Blocks
Writing of memory data is performed in either byte or word increments typically within 9 s, a 15% improvement over the LH28F008SA. Each block can be written and erased a minimum of 100,000 cycles. Systems can achieve 1,000,000 Block Erase Cycles by providing wear-leveling algorithms and graceful block retirement. These techniques have already been employed in many flash file systems and Hard Disk Drive designs. The LH28F016LL incorporates two Page Buffers of 256 Bytes (128 Words) each to allow page data writes. This feature can improve a system write performance by up to 4.8 times over previous flash memory devices. All operations are started by a sequence of Write commands to the device. Three Status Registers (described in detail later) and a RY/BY output pin provide information on the progress of the requested operation. While the LH28F008SA requires an operation to complete before the next operation can be requested, the LH28F016LL allows queuing of the next operation while the memory executes the current operation. This eliminates system overhead when writing several bytes in a row to the array or erasing several blocks at the same time. The LH28F016LL can also perform write operations to one block of memory while performing erase of another block. The LH28F016LL provides user-selectable block locking to protect code or data such as Device Drivers, PCMCIA card information, ROM-Executable O/S or Application Code. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the LH28F016LL has a master Write Protect pin (WP) which prevents any modifications to memory blocks whose lock-bits are set.
DESCRIPTION
The LH28F016LL is a high performance 16M (16,777,216 bit) block erasable non-volatile random access memory organized as either 1M x 16 or 2M x 8. The LH28F016LL includes thirty-two 64K (65,536) blocks or thirty-two 32-KW (32,768) blocks. A chip memory map is shown in Figure 3. The implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and results in greater product reliability and ease of use. Among the significant enhancements of the LH28F016LL:
* * * *
3 V Write/Erase Operation (3 V VPP) 3 V Low Power Capability Improved Write Performance Dedicated Block Write/Erase Protection
The LH28F016LL will be available in a 56-pin, 1.2 mm thick x 14 mm x 20 mm TSOP (Type I) package. This form factor and pinout allow for very high board layout densities. A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation.
5
LH28F016LL
16M (1M x 16, 2M x 8) Flash Memory
The LH28F016LL contains three types of Status Registers to accomplish various functions: * A Compatible Status Register (CSR) which is 100% compatible with the LH28F008SA Flash memory's Status Register. This register, when used alone, provides a straightforward upgrade capability to the LH28F016LL from a LH28F008SA-based design. * A Global Status Register (GSR) which informs the system of command Queue status. Page Buffer status, and overall Write Status Machine (WSM) status. * 32 Block Status Registers (BSRs) which provide block-specific status information such as the block lock-bit status. The GSR and BSR memory maps for Byte-Wide and Word-Wide modes are shown in Figures 4 and 5. The LH28F016LL incorporates an open drain RY/BY output pin. This feature allows the user to ORtie many RY/BY pins together in a multiple memory con figuration such as a Resident Flash Array. The LH28F016LL also incorporates a dual chipenable function with two input pins, CE0 and CE1. These pins have exactly the same functionality as the regulary chip-enable pin CE on the LH28F008SA. For minimum chip designs, CE1 may be tied to ground and use CE0 as the chip enable input. The LH28F016LL uses the logical combination of these two signals to enable or disable the entire chip. Both CE0 and CE1 must be active low to enable the device and if either one becomes inactive, the chip will be disabled. This feature, along with the open drain RY/BY pin, allows the system designer to reduce the number of control pins used in a large array of 16M devices. The BYTE pin allows either x8 or x16 read/writes to the LH28F016LL. BYTE at logic low selects 8-bit mode with address A0 selecting between low byte and high byte. On the other hand, BYTE at logic high enables 16-bit operation with address A1 becoming the lowest order address and address A0 is not used (don't care). A device diagram is shown in Figure 1. The LH28F016LL is specified for a maximum access time (tACC)150 ns, in operating voltage 2.7 V to 3.6 V and in operating temperature 0C to +70C. The LH28F016LL incorporates an Automatic Power Saving (APS) feature which substantially reduces the active current when the device is in static mode of operation (address not switching). In APS mode, the typical ICC current is 1 mA at 3.0 V. A Deep Power-Down mode of operation is invoked when the RP (called PWD on the LH28F008SA) pin transitions low. This mode brings the device power consumption to less than 5 A typically, and provides additional write protection by acting as a device reset pin during power transitions. A reset time of 480 ns is required from RP switching high until outputs are again valid. In the Deep Power-Down state, the WSM is reset 6
MEMORY MAP
1FFFFFH 1F0000H 1EFFFFH 1E0000H 1DFFFFH 1D0000H 1CFFFFH 1C0000H 1BFFFFH 1B0000H 1AFFFFH 1A0000H 19FFFFH 190000H 18FFFFH 180000H 17FFFFH 170000H 16FFFFH 160000H 15FFFFH 150000H 14FFFFH 140000H 13FFFFH 130000H 12FFFFH 120000H 11FFFFH 110000H 10FFFFH 100000H 0FFFFFH 0F0000H 0EFFFFH 0E0000H 0DFFFFH 0D0000H 0CFFFFH 0C0000H 0BFFFFH 0B0000H 0AFFFFH 0A0000H 09FFFFH 090000H 08FFFFH 080000H 07FFFFH 070000H 06FFFFH 060000H 05FFFFH 050000H 04FFFFH 040000H 03FFFFH 030000H 02FFFFH 020000H 01FFFFH 010000H 00FFFFH 000000H
64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
28F016LLT-3
Figure 3. LH28F016LL Memory Map (any current operation will abort) and the CSR, GSR and BSR registers are cleared. A CMOS Standby mode of operation is enabled when either CE0 or CE1 transitions high and RP stays high with all input control pins at CMOS levels. In this mode, the device typically draws an ICC standby current of 10 A.
16M (1M x 16, 2M x 8) Flash Memory
LH28F016LL
Extended Status Registers Memory Map
x8 MODE RESERVED GSR RESERVED BSR31 RESERVED RESERVED
A[20:0]
1F0006H 1F0005H 1F0004H 1F0003H 1F0002H 1F0001H 1F0000H
x16 MODE
A[20:1] (NOTE)
RESERVED GSR RESERVED BSR31 RESERVED RESERVED F8003H
F8002H
F8001H
. . .
RESERVED
. . .
RESERVED
F8000H
010002H 000006H RESERVED GSR RESERVED BSR0 RESERVED RESERVED 000005H 000004H 000003H 000002H 000001H 000000H
28F016LLT-4
08001H 00003H
RESERVED GSR RESERVED BSR0 RESERVED RESERVED
00002H
00001H 00000H
Figure 4. Extended Status Register Memory Map (Byte-Wide Mode)
NOTE: In word-wide mode A0 don't care, address values are ignored A0. 28F016LLT-5
Figure 5. Extended Status Register Memory Map (Word-Wide Mode)
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LH28F016LL
16M (1M x 16, 2M x 8) Flash Memory
BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS Bus Operations for Word-Wide Mode (BYTE = VIH)
MODE RP CE 1 CE 0 OE WE A1 DQ0 - DQ15 RY /BY NOTE
Read Output Disable Standby Deep Power-Down Manufacturer ID Device ID Write
VIH VIH VIH VIL VIH VIH VIH
VIL VIL VIL VIH VIH X VIL VIL VIL
VIL VIL VIH VIL VIH X VIL VIL VIL
VIL VIH X X VIL VIL VIH
VIH VIH X X VIH VIH VIL
X X X X VIL VIH X
DOUT High-Z High-Z High-Z 00B0H 6688H DIN
X X X VOH VOH VOH X
1, 2 1, 6 1, 6 1, 3 4 4 1, 5, 6
Bus Operations For Byte-Wide Mode (BYTE = VIL)
MODE RP CE 1 CE 0 OE WE A0 DQ0 - DQ7 RY /BY NOTE
Read Output Disable Standby Deep Power-Down Manufacturer ID Device ID Write
VIH VIH VIH VIL VIH VIH VIH
VIL VIL VIL VIH VIH X VIL VIL VIL
VIL VIL VIH VIL VIH X VIL VIL VIL
VIL VIH X X VIL VIL VIH
VIH VIH X X VIH VIH VIL
X X X X VIL VIH X
DOUT High-Z High-Z High-Z B0H 88H DIN
X X X VOH VOH VOH X
1, 2 1, 6 1, 6 1, 3 4 4 1, 5, 6
NOTES: 1. X can be VIH or VIL for address or control pins except for RY/BY, which is either VOL or VOH . 2. RY/BY output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode, RY/BY will be at VOH if it is tied to VCC through a resistor. When the RY/BY at VOH is independent of OE while a WSM operation is in progress. 3. RP at GND 0.2 V ensures the lowest deep power-down current. 4. A0 and A1 at VIL provide manufacturer ID codes in x8 and x16 modes respectively. All other addresses are set to zero. A0 and A1, at VIH provide device ID codes in x8 and x16 modes respectively. All other addresses are set to zero. 5. Commands for different Erase operations, Data Write operations of Lock-Block operations can only be successfully completed when VPP = VPPH. 6. While the WSM is running, RY/BY in Level-Mode (default) stays at VOL until all operations are complete. RY/BY goes to VOH when the WSM is not busy or in erase suspend mode.
8
16M (1M x 16, 2M x 8) Flash Memory
LH28F016LL
LH28F008SA-Compatible Mode Command Bus Definitions
FIRST BUS CYCLE COMMAND OPER. ADDRESS DATA OPER. ADDRESS DATA SECOND BUS CYCLE NOTE
Read Array Intelligent Identifier Read Compatible Status Register Clear Status Register Word/Byte Write Alternate Word/Byte Write Block Erase/Confirm Erase Suspend/Resume
ADDRESS AA = Array Address BA = Block Address IA = Identifier Address WA = Write Address X = Don't Care
Write Write Write Write Write Write Write Write
DATA AD = Array Data CSRD = CSR Data ID = Identifier Data WD = Write Data
X X X X X X X X
FFH 90H 70H 50H 40H 10H 20H B0H
Read Read Read
AA IA X
AD ID CSRD 1 2 3
Write Write Write Write
WA WA BA X
WD WD D0H D0H
NOTES: 1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes. 2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations. 3. Clears CSR.3, CSR.4, and CSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits. See Status register definitions. 4. While device performs Block Erase, if you issue Erase Suspend command (B0H), be sure to confirm ESS (Erase-Suspend-Status) is set to 1 on compatible status register. In the case, ESS bit was not set to 1, also completed the Erase (ESS = 0, WASM = 1), be sure to issue Resume command (D0H) after completed next Erase command. Beside, when the Erase Suspend command is issued, while the device is not in Erase, be sure to issue Resume command (D0H) after the next erase completed. When you use Erase Suspend/ Resume command, we recommend to issue serial Block Erase command (20H, D0H) and Resume command (D0H). (Refer to Performance Enhancement Command Bus Definitions.)
9
LH28F016LL
16M (1M x 16, 2M x 8) Flash Memory
LH28F800SU Performance Enhancement Command Bus Definitions
FIRST BUS CYCLE COMMAND MODE OPER. ADDR. DATA OPER. ADDR. DATA OPER. ADDR. DATA SECOND BUS CYCLE THIRD BUS CYCLE NOTE
Read Extended Status Register Page Buffer Swap Read Page Buffer Single Load to Page Buffer x8 Sequential Load to Page Buffer x16 x8 x16 Two-Byte Write Block Erase/Confirm Lock Block/Confirm Upload Status Bits/Confirm Upload Device Information Erase All Unlocked Blocks/Confirm RY /BY Enable to Level-Mode RY /BY Pulse-OnWrite RY /BY Pulse-OnErase RY /BY Disable Sleep Abort
ADDRESS BA = Block Address PA = Page Buffer Address RA = Extended Register Address WA = Write Address X = Don't Care
Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write
X X X X X X X X X X X X X X X X X X X X
71H 72H 75H 74H E0H E0H 0CH 0CH FBH 20H 77H 97H 99H A7H 96H 96H 96H 96H F0H 80H
Read
RA
GSRD BSRD
1 7
Read Write Write Write Write Write Write Write Write Write Write Write Write Write Write Write
PA PA X X A0 X A0 BA BA X X X X X X X
PD PD BCL WCL BC (L, H) WCL WD (L, H) D0H D0H D0H D0H D0H 01H 02H 03H 04H 8 8 8 8 2 Write Write Write Write Write Write X X WA WA WA X BCH WCH BC (H, L) WCH WD (H, L) D0H 4, 6, 10 4, 5, 6, 10 3, 4, 9, 10 4, 5, 10 3 11
Page Buffer Write to Flash
x8
DATA AD = Array Data PD = Page Buffer Data BSRD = BSR Data GSRD = GSR Data WC (L, H) = Word Count (Low, High) BC (L, H) = Byte Count (Low, High) WD (L, H) = Write Data (Low, High)
10
16M (1M x 16, 2M x 8) Flash Memory
LH28F016LL
NOTES: 1. RA can be the GSR address or any BSR address. See Figure 4.1 and 4.2 for Extended Status Register Memory Maps. 2. Upon device power-up, all BSR lock-bits come up locked. The Uploaded Status Bits command must be written to reflect the actual lock-bit status. 3. A0 is automatically complemented to load second byte of data. BYTE must be at VIL. A0 value determines which WD/BC is supplied first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH. 4. BCH/WCH must be at 00H for this product because of the 256-Byte (128 Word) Page Buffer size and to avoid writing the Page Buffer contents into more than one 256-Byte segment within an array block. They are simply shown for future Page Buffer expandability. 5. In x16 mode, only the lower byte DQ0 - DQ 7 is used for WCL and WCH. The upper byte DQ8 - DQ15 is a don't care. 6. PA and PD (Whose count is given in cycles 2 and 3) are supplied starting in the 4th cycle which is not shown. 7. This command allows the user to swap between available Page Buffers (0 or 1). 8. These commands reconfigure RY/BY output to one of two pulse-modes or enable and disable the RY/BY function. 9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer. Refer to the LH28F016SU User's Manual. 10. BCL = 00H corresponds to a Byte count of 1. Similarly, WCL = 00H corresponds to a Word count of 1. 11. Unless you issue erase suspend command, it is not necessary to input D0H on third bus cycle.
Compatible Status Register
WSMS 7 ESS 6 ES 5 DWS 4 VPPS 3 R 2 R 1 R 0
CSR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy CSR.6 = ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase in Progress/Completed CSR.5 = ERASE STATUS (ES) 1 = Error in Block Erasure 0 = Successful Block Erase CSR.4 = DATA-WRITE STATUS (DWS) 1 = Error in Data Write 0 = Data Write Successful CSR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK
NOTES: 1. RY/BY output or WSMS bit must be checked to determine completion of an operation (Erase Suspend, Erase or Data Write) before the appropriate Status bit (ESS, ES or DWS) is checked for success. 2. If DWS and ES are set to `1' during an erase attempt, an improper command sequence was entered. Clear the CSR and attempt the operation again. 3. The VPPS bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates VPP's level only after the Data-Write or Erase command sequences have been entered, and informs the system if VPP has not been switched on. VPPS is not guaranteed to report accurate feedback between VPPL and VPPH. 4. CSR.2 - CSR.0 = Reserved for future enhancements. These bits are reserved for future use and should be masked out when polling the CSR.
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LH28F016LL
16M (1M x 16, 2M x 8) Flash Memory
GLOBAL STATUS REGISTER
WSMS 7 OSS 6 DOS 5 DSS 4 QS 3 PBAS 2 PBS 1 PBSS 0
GSR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy GSR.6 = OPERATION SUSPEND STATUS (OSS) 1 = Operation Suspended 0 = Operation in Progress/Completed GSR.5 = DEVICE OPERATION STATUS (DOS) 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running GSR.4 = DEVICE SLEEP STATUS(DSS) 1 = Device in Sleep 0 = Device Not in Sleep MATRIX 5/4 00 01 10 11
NOTES: 1. RY/BY output or WSMS bit must be checked to determine completion of an operation (Block Lock, Suspend, any RY/ BY reconfiguration, Upload Status Bits, Erase or Data Write) before the appropriate Status bit (OSS or DOS) is checked for success. 2. If operation currently running, then GSR.7 = 0. 3. If device pending sleep, then GSR.7 = 0. 4. Operation aborted: Unsucccessful due to Abort command. 5. The device contains two Page Buffers. 6. Selected Page Buffer is currently busy with WSM operation. 7. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block. GSR.7 provides indication when all queued operations are completed.
= Operation Successful or Currently Running = Device in Sleep Mode or Pending Sleep = Operation Unsuccesful = Operation Unsuccessful or Aborted
GSR.3 = QUEUE STATUS (QS) 1 = Queue Full 0 = Queue Available GSR.2 = PAGE BUFFER AVAILABLE STATUS (PBAS) 1 = One or Two Page Buffers Available 0 = No Page Buffer Available GSR.1 = PAGE BUFFER STATUS (PBS) 1 = Selected Page Buffer Ready 0 = Selected Page Buffer Busy GSR.0 = PAGE BUFFER SELECT STATUS (PBSS) 1 = Page Buffer 1 Selected 0 = Page buffer 0 Selected
12
16M (1M x 16, 2M x 8) Flash Memory
LH28F016LL
BLOCK STATUS REGISTER
BS 7 BLS 6 BOS 5 BOAS 4 QS 3 VPPS 2 R 1 R 0
BSR.7 = 1BLOCK STATUS (BS) 1 = Ready 0 = Busy BSR.6 = BLOCK-LOCK STATUS (BLS) 1 = Block Unlocked for Write/Erase 0 = Block Locked for Write/Erase BSR.5 = BLOCK OPERATION STATUS (BOS) 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running BSR.4 = BLOCK OPERATION ABORT STATUS (BOAS) 1 = Operation Aborted 0 = Operation Not Aborted MATRIX 5/4 00 01 10 11
NOTES: 1. RY/BY output or BS bit must be checked to determine completion of an operation (Block Lock, Suspend, Erase or Data Write) before the appropriate Status bits (BOS, BLS) is checked for success. 2. The BOAS bit will not be set until BSR.7 = 1. 3. Operation halted via Abort command. 4. BSR.1-0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the BSRs. 5. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block. GSR.7 provides indication when all queued operations are completed.
= Operation Successful or Currently Running = Not a valid Combination = Operation Unsuccessful = Operation Aborted
BSR.3 = QUEUE STATUS (QS) 1 = Queue Full 0 = Queue Available BSR.2 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK
13
LH28F016LL
16M (1M x 16, 2M x 8) Flash Memory
ELECTRICAL SPECIFICATIONS1 Absolute Maximum Ratings*
Temperature under bias ......................... 0C to +80C Storage temperature ......................... -65C to +125C
*WARNING: Stressing the device beyond
the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
VCC = 3.3 V 0.3 V Systems4
SYMBOL PARAMETER MIN. MAX. UNITS TEST CONDITIONS NOTE
TA VCC VPP V I IOUT
Operating Temperature, Commercial VCC with Respect to GND VPP Supply Voltage with Respect to GND Voltage on any Pin (Except VCC, VPP) with Respect to GND Current into any Non-Supply Pin Output Short Circuit Current
0 -0.2 -0.2 -0.5
70.0 7.0 7.0 VCC + 0.5 30 100.0
C V V V mA mA
Ambient Temperature
1 2 2 2
3
NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Minimum C voltage is -0.5 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum C voltage on input/output pins is V CC + 0.5 V which, during transitions, may overshoot to VCC + 2.0 V for periods < 20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. 4. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.
Capacitance For 3.3 V Systems
SYMBOL PARAMETER TYP.
6
MAX.
8
UNITS
TEST CONDITIONS
NOTE
CIN COUT CLOAD
Capacitance Looking into an Address/Control Pin Capacitance Looking into an Output Pin Load Capacitance Driven by Outputs for Timing Specifications Equivalent Testing Load Circuit
pF pF pF ns
TA = 25C, f = 1.0 MHz TA = 25C, f = 1.0 MHz For VCC = 3.3 V 0.3 V 50 transmission line delay
1 1 1
8
12 50 2.5
NOTE: 1. Sampled, not 100% tested.
14
16M (1M x 16, 2M x 8) Flash Memory
LH28F016LL
Timing Nomenclature
All 3.3 V system timings are measured from where signals cross 1.5 V. For 5.0 V systems use the standard JEDEC cross point definitions. Each timing parameter consists of 5 characters. Some common examples are defined below: tCE tOE tAS tDH tELQV tGLQV time (t) from CE (E) going low (L) to the outputs (Q) becoming valid (V) time (t) from OE (G) going low (L) to the outputs (Q) becoming valid (V) time (t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
tACC tAVQV
tAVWH time (t) from address (A) valid (V) to WE (W) going high (H) tWHDX time (t) from WE (W) going high (H) to when the data (D) can become undefined (X)
PIN CHARACTERS
PIN STATES
A D Q E G W P R V 3V
Address Inputs Data Inputs Data Outputs CE (Chip Enable) OE (Output Enable) WE (Write Enable) RP (Deep Power-Down Pin) RY /BY (Ready/Busy) Any Voltage Level VCC at 3.0 V Min.
H L V X Z
High Low Valid Driven, but not necessarily valid High Impedance
3.0 INPUT 1.5 0.0
2.5 ns OF 50 TRANSMISSION LINE
TEST POINTS 1.5 OUTPUT
FROM OUTPUT UNDER TEST
TEST POINT
NOTE: AC test inputs are driven at 3.0 V for a Logic '1' and 0.0 V for a Logic '0'. Input timing begins and output timing ends at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns. 28F016LLT-6
TOTAL CAPACITANCE = 50 pF
28F016LLT-7
Figure 6. Transient Input/Output Reference Waveform (VCC = 3.3 V)
Figure 7. Transient Equivalent Testing Load Circuit (VCC = 3.3 V)
15
LH28F016LL
16M (1M x 16, 2M x 8) Flash Memory
DC Characteristics
VCC = 3.3 V 0.3 V, TA = 0C to +70C
SYMBOL PARAMETER TYP. MIN. MAX. UNITS TEST CONDITIONS NOTE
IIL ILO
Input Load Current Output Leakage Current
1 10
A A
VCC = VCC MAX., VIN = VCC or GND VCC = VCC MAX., VIN = VCC or GND VCC = VCC MAX., CE 0, CE 1, RP = VCC 0.2 V BYTE, WP, 3/5 = VCC 0.2 V or GND 0.2 V VCC = VCC MAX., CE 0, CE 1, RP = VIH BYTE, WP, 3/5 = VIH or VIL RP = GND 0.2 V VCC = VCC MAX., CMOS: CE 0, CE 1 = GND 0.2 V BYTE = GND 0.2 V or VCC 0.2 V Inputs = GND 0.2 V or VCC 0.2 V TTL: CE 0, CE 1 = VIL, BYTE = VIL or VIH Inputs = VIL or VIH f = 8 MHz, IOUT = 0 mA VCC = VCC MAX., CMOS: CE 0, CE 1 = GND 0.2 V BYTE = VCC 0.2 V or GND 0.2 V Inputs = GND 0.2 V or VCC 0.2 V TTL: CE 0, CE 1 = VIL, BYTE = VIH or VIL Inputs = VIL or VIH f = 4 MHz, IOUT = 0 mA Word/Byte Write in Progress Block Erase in Progress CE 0, CE 1 = VIH Block Erase Suspended VPP VCC RP = GND 0.2 V
1 1
4 ICCS VCC Standby Current 1 VCC Deep Power-Down Current
8
A
1, 4
4
mA
ICCD
1
5
A
1
ICCR1
VCC Read Current
30
35
mA
1, 3, 4
ICCR2
VCC Read Current
15
20
mA
1, 3, 4
ICCW ICCE ICCES IPPS IPPD
VCC Write Current VCC Block Erase Current VCC Erase Suspend Current VPP Standby Current VPP Deep Power-Down Current
8 6 3 0.2 0.2
12 10 6 5 5
mA mA mA A A
1 1 1, 2 1 1
16
16M (1M x 16, 2M x 8) Flash Memory
LH28F016LL
DC Characteristics (Continued)
VCC = 3.3 V 0.3 V, TA = 0C to +70C
SYMBOL PARAMETER TYPE MIN. MAX. UNITS TEST CONDITIONS NOTE
IPPR IPPW IPPE IPPES VIL VIH VOL VOH1
VPP Read Current VPP Write Current VPP Erase Current VPP Erase Suspend Current Input Low Voltage Input High Voltage Output Low Voltage 2.4 Output High Voltage VCC - 0.2 VPP during Normal Operations VPP during Write/Erase Operations VCC Erase/Write Lock Voltage 5.0 0.0 4.5 2.0 -0.3 2.0 50 30
5 ** 65 200 0.8 VCC + 0.3 0.4
A mA mA A V V V V V
VPP > VCC VPP = VPPH, Word/Byte Write in Progress VPP = VPPH, Block Erase in Progress VPP = VPPH, Block Erase Suspended
1 1 1 1
VCC = VCC MIN. and IOL = 4 mA IOH = 2.0 mA VCC = VCC MIN. IOH = 100 A VCC = VCC MIN.
VOH
2
VPPL VPPH VLKO
5.5 5.5
V V V
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = VPP = 3.3 V, T = 25C. All IPP stands for outside inductor's current. 2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Automatic Power Saving (APS) reduces ICCR to less than 1 mA in Static operation. **To be Determined
VCC LX
28F016LLT-8
Figure 8. Transient Equivalent Testing Load Circuit (VCC = 3.3 V)
17
LH28F016LL
16M (1M x 16, 2M x 8) Flash Memory
AC Characteristics - Read Only Operations1
VCC = 3.3 V, TA = 0C to +70C
SYMBOL PARAMETER VCC = 3.3 V 0.3 V MIN. MAX. UNITS NOTE
tAVAV tAVEL tAVGL tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH tFLQV tFHQV tFLQZ tELFL tELFH
Read Cycle Time Address Setup to CE Going Low Address Setup to OE Going Low Address to Output Delay CE to Output Delay RP High to Output Delay OE to Output Delay CE to Output in Low Z CE to Output in High Z OE to Output in Low Z OE to Output in High Z Output Hold from Address, CE or OE change, whichever occurs first
BYTE to Output Delay
100
ns
ns 3, 4
10 0
100
ns ns ns ns ns ns 50 ns ns 30 ns ns
120 ns
3, 4
100 620 45 0
2
2
3 3 3 3 3
3
0
0
BYTE Low to Output in High Z CE Low to BYTE High or Low
30
5
ns ns
3 3
NOTES: 1. See AC Input/Output Reference Waveforms for timing measurements. 2. OE may be delayed up to t ELQV - tGLQV after the falling edge of CE without impact on tELQV. 3. Sampled, not 100% tested. 4. This timing parameter is used to latch the correct BSR data onto the outputs.
18
16M (1M x 16, 2M x 8) Flash Memory
LH28F016LL
VCC POWER-UP
STANDBY
DEVICE AND ADDRESS SELECTION
OUTPUTS ENABLED
DATA VALID
ADDRESSES (A)
VIH VIL
...
VCC STANDBY POWER-DOWN
ADDRESSES STABLE tAVAV
...
CEX (E) (NOTE)
VIH VIL tAVEL VIH VIL tAVGL
...
tEHQZ
OE (G)
...
tGHQZ
WE (W)
VIH VIL tGLQV tELQV tGLQX tELQX VOH VOL tAVQV 5.0 V GND tPHQV HIGH-Z
...
tOH
...
VALID OUTPUT
DATA (D/Q)
HIGH-Z
...
VCC
RP (P)
VIH VIL
NOTE: CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH.
28F016LLT-9
Figure 9. Read Timing Waveforms
19
LH28F016LL
16M (1M x 16, 2M x 8) Flash Memory
ADDRESSES (A)
VIH VIL
...
ADDRESSES STABLE tAVAV
...
CEX (E) (NOTE)
VIH VIL tAVEL = tELFL VIH VIL
...
tEHQZ
OE (G)
tAVEL
tELFL tAVGL tFLQV = tAVQV tGLQV
...
tGHQZ
BYTE (F)
VIH VIL tELQV tGLQX tELQX VOH VOL tAVQV tFLQZ VOH VOL HIGH-Z HIGH-Z
...
tOH
...
DATA OUTPUT
DATA (DQ0 - DQ7)
...
DATA OUTPUT
HIGH-Z
DATA (DQ8 - DQ15)
DATA OUTPUT
HIGH-Z
NOTE: CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH.
28F016LLT-10
Figure 10. BYTE Timing Waveforms
20
16M (1M x 16, 2M x 8) Flash Memory
LH28F016LL
VCC POWER UP RP (P)
3.3 V VCC 0V 3.0 V
3.3 V
tPL
ADDRESS (A) tAVQV
VALID tAVQV
VALID
DATA (Q) tPHQV
VALID
VALID
tPHQV
28F016LLT-11
Figure 11. VCC Power-Up and RP Reset Waveforms
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
NOTE
tPL tAVQV tPHQV
RP Low to VCC at 3.0 V Minimum Address Valid to Data Valid for VCC = 2.7 V to 3.6 V RP High to Data Valid for VCC = 2.7 V to 3.6 V
0 ** **
s ns ns
1 2 2
NOTES: CE0, CE1 and OE are switched low after Power-Up. 1. The power supply may start to switch concurrently with RP going Low. 2. Refer to the AC Characteristics Read Only Operations for detail information. **To be Determined
21
LH28F016LL
16M (1M x 16, 2M x 8) Flash Memory
AC Characteristics for WE - Controlled Command Write Operations1
VCC = 3.3 V, TA = 0C to +70C
SYMBOL PARAMETER TYP. MIN. MAX. UNITS NOTE
tAVAV tVPWH tPHEL tELWL tAVWH tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tGHWL tWHRL tRHPL tPHWL tWHGL tQVVL tWHQV1 tWHQV2
Write Cycle Time VPP Setup to WE Going High RP Setup to CE Going Low CE Setup to WE Going Low Address Setup to WE Going High Data Setup to WE Going High WE Pulse Width Data Hold from WE High Address Hold from WE High CE Hold from WE High WE Pulse Width High Read Recovery before Write WE High to RY /BY Going Low RP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY /BY High RP High Recovery to WE Going Low Write Recovery before Read VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY /BY High Duration of Word/Byte Write Operation Duration of Block Erase Operation **
100 100 480 10 65 65 75 10 10 10 35 0 100 0 1 95 0 ** **
ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s s 4, 5 4 3 2 2 2, 6 2, 6 3
NOTES: CE is defined as the latter of CE0 or CE1 going Low or the first of CE0 or CE1 going High. 1. Read timing during write and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, but not 100% tested. 4. Write/Erase durations are measured to valid Status Register (CSR) Data. 5. Word/Byte write operations are typically performed with 1 Programming Pulse. 6. Address and Data are latched on the rising edge of CE for all Command Write Operations. **To be Determined
22
16M (1M x 16, 2M x 8) Flash Memory
LH28F016LL
WRITE VALID WRITE ADDRESS AND DATA AUTOMATED DATA-WRITE (DATA-WRITE) OR DATA-WRITE OR ERASE ERASE CONFIRM OR ERASE DEEP COMMAND DELAY POWER-DOWN SETUP COMMAND
WRITE READ EXTENDED REGISTER COMMAND
READ EXTENDED STATUS REGISTER DATA
ADDRESSES (A) VIH (NOTE 1) VIL tAVAV
AIN tAVWH tWHAX (NOTE 3)
A = RA
READ COMPATIBLE STATUS REGISTER DATA
ADDRESSES (A) VIH (NOTE 2) VIL tAVAV CEX (E) VIH (NOTE 4) V IL tWHEH tELWL VIH VIL tWHWL VIH VIL tWLWH tWHDX tDVWH DATA (D/Q) VIH VIL HIGH-Z tPHWL VOH VOL DIN
AIN tAVWH tWHAX
A = RA
tWHGL
OE (G)
tWHQV 1, 2
tGHWL
WE (W)
DIN tWHRL
DIN
DOUT
DIN
RY/BY (R)
tRHPL
V RP (P) VIH IL tVPWH VPPH VPPL
(NOTE 5) tQVVL
VPP (V)
NOTES: 1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD. 2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD. 3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations. 4. CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH. 5. RP low transition is only to show tRHPL; not valid for above Read and Write cycles.
28F016LLT-12
Figure 12. AC Waveforms for Command Write Operations
23
LH28F016LL
16M (1M x 16, 2M x 8) Flash Memory
AC Characteristics for CE - Controlled Command Write Operations1
VCC = 3.3 V 0.3 V, TA = 0C to +70C
SYMBOL PARAMETER TYP. MIN. MAX. UNITS NOTE
tAVAV tPHWL tVPEH tWLEL tAVEH tDVEH tELEH tEHDX tEHAX tEHWH tEHEL tGHEL tEHRL tRHPL tPHEL tEHGL tQVVL tEHQV1 tEHQV2
Write Cycle Time RP Setup to WE Going Low VPP Set up to CE Going High WE Setup to CE Going Low Address Setup to CE Going High Data Setup to CE Going High CE Pulse Width Data Hold from CE High Address Hold from CE High WE Hold from CE High CE Pulse Width High Read Recovery before Write CE High to RY /BY Going Low RP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY /BY High RP High Recovery to CE Going Low Write Recovery before Read VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY /BY High Duration of Word/Byte Write Operation Duration of Block Erase Operation **
100 480 100 0 75 75 75 10 10 10 45 0 100 0 1 95 0 ** **
ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s s 4, 5 4 3 2 2 2, 6 2, 6 3 3
NOTES: CE is defined as the latter of CE0 or CE1 going Low or the first of CE0 or CE1 going High. 1. Read timing during write and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, but not 100% tested. 4. Write/Erase durations are measured to valid Status Register (CSR) Data. 5. Word/Byte write operations are typically performed with 1 Programming Pulse. 6. Address and Data are latched on the rising edge of CE for all Command Write Operations. **To be Determined
24
16M (1M x 16, 2M x 8) Flash Memory
LH28F016LL
WRITE VALID WRITE ADDRESS AND DATA AUTOMATED DATA-WRITE (DATA-WRITE) OR DATA-WRITE OR ERASE ERASE CONFIRM OR ERASE DEEP COMMAND DELAY POWER-DOWN SETUP COMMAND
WRITE READ EXTENDED REGISTER COMMAND
READ EXTENDED STATUS REGISTER DATA
ADDRESSES (A) VIH (NOTE 1) VIL tAVAV
AIN tAVEH tEHAX (NOTE 3)
A = RA
READ COMPATIBLE STATUS REGISTER DATA
ADDRESSES (A) VIH (NOTE 2) VIL tAVAV VIH VIL tEHWH tWLEL VIH VIL tEHEL CEX (E) VIH (NOTE 4) VIL tELEH tEHDX tDVEH DATA (D/Q) VIH VIL HIGH-Z tPHEL VOH VOL DIN
AIN tAVEH tEHAX
WE (W)
tEHGL
OE (G)
tEHQV 1, 2
tGHEL
DIN tEHRL
DIN
DOUT
DIN
RY/BY (R)
tRHPL
RP (P)
VIH VIL tVPEH
(NOTE 5) tQVVL
VPP (V)
VPPH VPPL
NOTES: 1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD. 2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD. 3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations. 4. CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH. 5. RP low transition is only to show tRHPL; not valid for above Read and Write cycles.
28F016LLT-13
Figure 13. AC Waveforms for Command Write Operations
25
LH28F016LL
16M (1M x 16, 2M x 8) Flash Memory
AC Characteristics for Page Buffer Write Operations1
VCC = 3.3 V 0.3 V, TA = 0C to +70C
SYMBOL PARAMETER TYP. MIN. MAX. UNITS NOTE
tAVAV tELWL tAVWL tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tGHWL tWHGL
Write Cycle Time CE Setup to WE Going Low Address Setup to WE Going Low Data Setup to WE Going High WE Pulse Width Data Hold from WE High Address Hold from WE High CE Hold from WE High WE Pulse Width High Read Recovery before Write Write Recovery before Read
120 10 0 75 75 10 10 10 45 0 95
ns ns ns ns ns ns ns ns ns ns ns 2 2 3 2
NOTES: CE is defined as the latter of CE0 or CE1 going Low or the first of CE0 or CE1 going High. 1. These are WE controlled write timings, equivalent CE controlled write timings apply. 2. Sampled, but not 100% tested. 3. Address must be valid during the entire WE Low pulse.
26
16M (1M x 16, 2M x 8) Flash Memory
LH28F016LL
tWHEH
CEX (E) tELWL
WE (W) tAVWL tWLWH tWHAX tWHWL
ADDRESSES
VALID tDVWH HIGH-Z tWHDX
DATA (D/Q)
DIN
28F016LLT-14
Figure 14. Page Buffer Write Timing Waveforms
Erase and Word/Byte Write Performance
VCC = 3.3 V 0.3 V, TA = 0C to +70C
SYMBOL PARAMETER TYP.(1) MIN. MAX. UNITS TEST CONDITIONS NOTE
tWHRH1 tWHRH2 tWHRH3
Word/Byte Write Time Block Write Time Block Write Time Block Erase Time Full Chip Erase Time
12 0.8 0.4 ** ** 2.1 1.0 10
s s s s s Byte Write Mode Word Write Mode
2
2 2 2 2
NOTES: 1. 25C, VPP = 3.3 V Sampled. 2. Excludes System-Level Overhead. **To be Determined
27
LH28F016LL
16M (1M x 16, 2M x 8) Flash Memory
56TSOP (TSOP056-P-1420)
1 56
0.50 [0.020] TYP.
0.28 [0.011] 0.12 [0.005] 28 29
0.13 [0.005] 0.49 [0.019] 0.39 [0.015] 20.30 [0.799] 19.70 [0.776] 18.60 [0.732] 18.20 [0.717] 0.18 [0.007] 0.08 [0.003] PACKAGE BASE PLANE 19.30 [0.760] 18.70 [0.736] MAXIMUM LIMIT MINIMUM LIMIT 0.22 [0.009] 0.02 [0.001] 1.10 [0.043] 0.90 [0.035] 1.19 [0.047] MAX.
DIMENSIONS IN MM [INCHES]
14.20 [0.559] 13.80 [0.543]
56TSOP
ORDERING INFORMATION
LH28F016LL Device Type T -## Package Speed 12 120 15 150 Access Time (ns) 56-pin, 1.2 mm x 14 mm x 20 mm TSOP (Type I) (TSOP056-P-1420) 16M (1M x 16, 2M x 8) Flash Memory Example: LH28F016LLT-12 (16M (1M x 16, 2M x 8) Flash Memory, 120 ns, 56-pin TSOP)
28F016LLT-15
28
16M (1M x 16, 2M x 8) Flash Memory
LH28F016LL
LIFE SUPPORT POLICY SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation. WARRANTY SHARP warrants to Customer that the Products will be free from defects in material and workmanship under normal use and service for a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the failure to SHARP in writing) or, (ii) if SHARP is unable to repair or replace, SHARP will refund the purchase price of the Product upon its return to SHARP. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than SHARP. The warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE ARE SPECIFICALLY EXCLUDED. SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility for the use of any circuitry described; no circuit patent licenses are implied.
(R)
NORTH AMERICA
EUROPE
ASIA
SHARP Electronics Corporation Microelectronics Group 5700 NW Pacific Rim Blvd., M/S 20 Camas, WA 98607, U.S.A. Phone: (360) 834-2500 Telex: 49608472 (SHARPCAM) Facsimile: (360) 834-8903 http://www.sharpmeg.com
SHARP Electronics (Europe) GmbH Microelectronics Division Sonninstrae 3 20097 Hamburg, Germany Phone: (49) 40 2376-2286 Telex: 2161867 (HEEG D) Facsimile: (49) 40 2376-2232
SHARP Corporation Integrated Circuits Group 2613-1 Ichinomoto-Cho Tenri-City, Nara, 632, Japan Phone: (07436) 5-1321 Telex: LABOMETA-B J63428 Facsimile: (07436) 5-1532
(c)1997 by SHARP Corporation Issued May 1996
Reference Code SMT96120

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